Field
The present disclosure pertains to the reducing or minimizing current/power consumption in memory devices on which dynamic memory management (DMM) is implemented.
Background
FIG. 1 illustrates low-power state current/power consumption variations between memory devices as well as banks therein. In one example, a plurality of volatile memory devices 102, 104, and 106, such are random access memory (RAM) devices (e.g., RAM parts), may be included as part of a larger circuit or electronic device. Each volatile memory device 104 may be arranged as a plurality of memory banks 108, 110, and 112, e.g., within a single silicon die. Due to the nature of the silicon manufacturing process, there may be part-to-part power variations (e.g., device-to-device power variations) and bank-to-bank power variations within each memory device. That is, each volatile memory device may exhibit a different low-power state consumption (e.g., leakage current, dynamic power consumption, etc.), while each memory bank may also exhibit a different low-power state consumption.
Some processing systems seek to implement power management or conservation which may involve reducing power usage of some memory devices when idle. Dynamic Memory Management (DMM) is one such system.
FIG. 2 illustrates a traditional dynamic memory management (DMM) scheme. Here, a processing circuit 202 may be coupled to a plurality of volatile memory devices 204, 206, 208, 210 (e.g., RAM x 32), on dual channels Ch0 and Ch1 (e.g., channel 0 and channel 1). During periods of prolonged idleness (e.g., overnight, in bags, etc.) available volatile memory is dynamically decreased (e.g., shutoff). Memory pages in upper volatile memory devices 204 and 208 are flushed if possible, or otherwise migrated to lower volatile memory devices 206 and 210. Here, it can be perceived that when entering DMM mode, data is migrated from a first plurality of volatile memory devices 204 and 208 on chip select 1 (cs1) to a second plurality of volatile memory devices 206 and 210 on chip select 0 (cs0). Once there are no active memory pages (e.g., block or segment of memory) in the memory devices controlled by chip select cs1 (i.e., upper volatile memory devices 204 and 208), those memory devices 204 and 208 coupled to chip select cs1 are transitioned to a Deep Power-down state to conserve power. However, this approach does not take into account the efficiency (e.g., low-power state current) of the memory devices 204 and 208 being powered-down and/or the memory devices 206 and 210 kept active.
Consequently, a more efficient method of power management for volatile memory devices is needed to further improve on the traditional Dynamic Memory Management approach.